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Efficient Implementation of Adaptive Filter Architecture Using Gate Level Modification for ECG Denoising

Abstract— A versatile channel assumes a critical part in clamor cancelation application. This paper introduces the gate level modified architectures for adaptive noise cancellation (ANC) using Matlab Simulink and Xilinx System generator and its implementation in XUP FPGA board. Gate level modification are done in Recursive Least square (RLS) filters to enhance the Signal to Noise ratio (SNR) and to optimize the VLSI parameters. The designed gate level modified structures are applied for noise cancellation in ECG Signals and Speech signals. The proposed gate level modified architectures shows better improvement in SNR, area and delay optimization respectively. From the results, it is clear that gate level modified RLS shows SNR improvement of 1.47% and 4.52% and shows area and combinational path reduction of 25.1% and 0.4% than basic RLS for 8-Tap filter respectively.

Index Terms— adaptive filter, ECG denoising, RLS, SNR, Power Line Interference.

V. Kavitha, P. Kaviya Priya, Tha.Sugapriyaa
Department of Electronics and Communication Engineering, M.Kumarsamy College of Engineering, India

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Cite: V. Kavitha, P. Kaviya Priya, Tha.Sugapriyaa, "Efficient Implementation of Adaptive Filter Architecture Using Gate Level Modification for ECG Denoising," Proceedings of 2018 the 8th International Workshop on Computer Science and Engineering, pp. 171-177, Bangkok, 28-30 June, 2018.