ISBN: 978-981-11-3671-9 DOI: 10.18178/wcse.2017.06.071
Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM
Abstract— This paper proposes a verification platform based on UVM for a 40Gbps high-speed serial
interface chip. Using the platform as basis, both the RTL codes and the relevant netlist after synthesis of the
40Gbps chip are fully tested to ensure the correctness of the chip’s functions. This guarantees the success of
the chip’s tap-out.
Index Terms— UVM, High-speed Serial Interface Chip, 40Gbps, Verification Platform.
Yuan Li, Zhengbin, PangLei Zhang, Hanqiang Cheng
College of Computer Science, National University of Defense Technology, CHINA
Cite: Yuan Li, Zhengbin, PangLei Zhang, Hanqiang Cheng, "Verification Platform of 40Gbps High-speed Serial Interface Chip Based on UVM," Proceedings of 2017 the 7th International Workshop on Computer Science and Engineering, pp. 417-421, Beijing, 25-27 June, 2017.