WCSE

Design and Implementation of DMA Transfer Through PCI Express Gen3 Interface Based on FPGA

Abstract— The future requirements for bandwidth and scalability of big data has gone beyond the performance of the second generation I/O interconnect. Peripheral component interconnect express (PCI Express)3.0 is the latest standard as one of the third generation I/O interconnect for expansion cards. The bit rate of this fully serial interface has reached 8 giga transfers per second(Gbps), which could meet the demand of future computing and communication platforms. In this paper, we designed and implemented the directly memory access (DMA) transfer of PCI Express Gen3 interface based on the Xilinx Virtex-7 FPGA Gen3 Integrated Block for PCI Express core. The proposed design has debugged and verified on the Xilinx Virtex-7 FPGA VC709 Connectivity Kit and could carry an average rate of 3.04GB/s, this design provides up to 300% improvement over the similar design based on PCI Express Gen2 interface.

Index Terms— FPGA, PCI Express 3.0, DMA Read, DMA Write.

Yufei Zhang, Hengzhu Liu, Xiaodong Yi, Xuan Zhu
Department of Computer, National University of Defense Technology, CHINA

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Cite: Yufei Zhang, Hengzhu Liu, Xiaodong Yi, Xuan Zhu, "Design and Implementation of DMA Transfer Through PCI Express Gen3 Interface Based on FPGA," 2015 The 5th International Workshop on Computer Science and Engineering-Information Processing and Control Engineering (WCSE 2015-IPCE), pp.696-704, Moscow, Russia, April 15-17, 2015.