ISBN: 978-981-09-5471-0 DOI: 10.18178/wcse.2015.04.115
Low Latency Mesh-based Hierarchical Network-on-Chip Structure
Abstract— With the integration of cores increasing, on chip network (NoC) latency and throughput get worse in traditional structures. This paper proposed a novel low latency hierarchical mesh-based network-on-chip (PHNoC) structure which uses three parameters to describe hierarchical topology for the size changing design, and three types of base clusters to construct multilevel structure. Experimental results demonstrated that the proposed structure had lower latency and higher throughput than traditional 2D mesh and conventional hierarchical NoC in different size systems, and the larger size the better performance it improved.
Index Terms— network-on-chip, Hierarchical interconnection, parameterized design, clustered network.
Gang Jian, Guo-dong Han, Yu-han Zhou
National Digital Switching System Engineering & Technological R&D Center, CHINA
Cite: Gang Jian, Guo-dong Han, Yu-han Zhou, "Low Latency Mesh-based Hierarchical Network-on-Chip Structure," 2015 The 5th International Workshop on Computer Science and Engineering-Information Processing and Control Engineering (WCSE 2015-IPCE), pp. 719-725, Moscow, Russia, April 15-17, 2015.